This invention relates to an instruction prefetching device for use in combination with a data or information processing system which includes an executing circuit for executing a sequence of instructions with each instruction processed successively in a plurality of stages.
Such an instruction prefetching device is for carrying out prefetch of at least one instruction from the sequence to form a queue of instructions in an instruction buffer and is already known. For example, an instruction prefetching device is disclosed in U.S. patent application Ser. No. 552,223 filed Nov. 16, 1983 (EPC Patent Application No. 83 111 451.7), by Syuichi Hanatani et al, including the present applicant, based on original Japanese Patent Application No. 201,550 of 1982 and others. Another instruction prefetching device is revealed in U.S. Pat. No. 4,607,229 which was issued Aug. 19, 1986 (EPC Patent Application No. 85 101 351.6), by the present applicant based on basic Japanese Patent Application No. 21,114 of 1984 and another basic Japanese patent application and which will herein be called an elder patent application. Incidentally, each of the above-mentioned plurality of stages is processed in a machine cycle. The stages include an executing stage of executing each instruction to provide a result of calculation which is indicated by the instruction in question.
According to the Hanatani et al patent application and the elder patent application, the instruction prefetching device includes a branch history table as a main element of a predicting arrangement. Responsive to an instruction address which is set in an instruction address register at a time, the predicting arrangement produces branch information obtained when an instruction having the instruction address was actually processed in the executing state prior to prefetch of the instruction under consideration. The predicting arrangement produces the branch information as predicted branch information. The instruction having the instruction address may be called a particular instruction merely for convenience of distinguishing the instruction in question from other instructions of the sequence.
The instruction prefetching device of the Hanatani et al patent application or of the elder patent application comprises a prediction checking or evaluating arrangement and a prefetch controlling arrangement. The prediction checking arrangement is coupled to the predicting arrangement and the executing circuit to carry out a check, immediately after the executing stage for the particular instruction, as regards whether the predicted branch information is correct or incorrect. The prefetch controlling arrangement is coupled to the predicting arrangement and the prediction checking arrangement to allow continuance of the prefetch in compliance with the predicted branch information when the predicted branch information is correct. When the predicted branch information is incorrect, the prefetch controlling arrangement corrects the continuance.
The instruction prefetching device of the Hanatani et al patent application is operable with only a short average loss cycle. The instruction prefetching device of the elder patent application is also operable with only a short average loss cycle and is particularly effective when the particular instruction is a branch on count instruction. It is, however, desirable to check as early as possible the predicted branch information and to decide whether the prefetch should be continued or corrected.